1. Technical Field
This disclosure generally relates to electronic design automation. More specifically, this disclosure relates to methods and apparatuses for zone-based leakage power optimization.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to efficiently perform leakage power optimization.
The leakage power of a circuit is the amount of power dissipated by the circuit when the circuit's metal-oxide-semiconductor (MOS) transistors are not switching on or off. Note that there is a tradeoff between the speed and the leakage power of a transistor. Specifically, transistors with a low threshold voltage (Vth) can be turned on and off faster than transistors with a high Vth because additional time is required to ramp-up the input voltage of these transistors toward Vth. However, transistors with a high Vth have less leakage power than transistors with a low Vth.
Unfortunately, conventional leakage-power optimization techniques are inefficient and/or generate poor quality of results (QoR). A circuit design's leakage power can be improved by replacing a logic gate with another functionally equivalent logic gate that dissipates a lower leakage power, if the transformation does not violate any design requirements. Specifically, for each transformation, conventional techniques typically perform a significant amount of computation to determine whether the transformation violates any timing metrics. Further, conventional leakage-power optimization techniques attempt to transform every logic gate of a circuit design in search for every opportunity to improve leakage power of the circuit design.